Electronic scoring system for bowling establishments

ABSTRACT

An automatic scoring system for a plurality of bowling lanes is disclosed which employs a central control unit including a general purpose mini-computer having a read-only memory programmed to control the processor in the computation and display of bowling scores. The system is constructed to be easily expanded by adding a player console and an electronic module for each added pair of bowling lanes. Bowling score sheet information is displayed on cathode ray tube display devices at player and proprietor locations. Pinfall information may be introduced manually or by automatic pinfall sensors.

for

[451 Sept. 23, 1975 l l 1 l Townsend Bolger..........

ABSTRACT or FirmEdward J. Norton; Carl V.

12/1970 Walker 2 Claims, 4 Drawing Figures Primary Examiner-Gareth D.Shaw Assistant Examiner-James D. Thomas Attorney, Agent Olson Anautomatic scoring system for a plurality of bowlin lanes is disclosedwhich employs a central control unit including a general purposemini-computer having a read-only memory programmed to control theprocessor in the computation and display of bowling scores. The systemis constructed to be easily expanded b adding a player console and anelectronic module each added pair of bowling lanes. Bowling score sheetinformation is displayed on cathode ray tube dis devices at player andproprietor locations. Pinfall information may be introduced manually orby automatic pinfall sensors.

54 s M m 1 53 557 332 2 PlNFALL SENSORS ELECTRONIC SCORING SYSTEM FORBOWLING ESTABLISHMENTS [75] Inventors: Joseph Bernard Fischer, PanoramaCity; Roy Atsushi Ito, Woodland Hills; Walter Lee Ross, Simi; MaureenRandall Schmidt, Chatsworth; Stanley Ward Stoddard, Canoga Park, all ofCalif.

[73] Assignee: RCA Corporation, New York, NY.

[22] Filed: June 22, 1973 [21] Appl. No.: 372,647

[52] US. Cl........ 273/54 C; 235/92 GA; 340/323 B [51] Int. Cl. A63D5/00; A63D 5/04 [58] Field of Search.....................

235/92 GA, 151; 273/54 C [56] References Cited UNITED STATES PATENTS3,375,352 3/1968 3,507,575 4/1970 Soule.......... 3,516,665 6/1970Danielson 3,531,117 9/1970 Preston.,............................,..

United States Patent Fischer et al.

. l t 1 GENERAL PURPOSE 5 MINI-COMPUTER TIMING 1 PLAYER CONSOLE- CENTRALCONTROL UNIT US Patent Sept. 23,1 975 Sheet 3 of4 3,907,290

US Patent Sept. 23,1975 Sheet 4 of4 3,907,290

* t/aus't" CONgROL XAR TIMING YAR V 47 MC G I FROM n CTR I AD ELECTRONICSCORING SYSTEM FOR BOWLING ESTABLISHMENTS BACKGROUND OF THE INVENTIONMany electromechanical and some electronic systems have been proposedfor accomplishing the automatic computation and display of bowlingscores. The rules which scores are computed in bowling contests are notsimple, and demands for inexpensive and reliable automatic scoringequipment have yet to be satisfied. The approach that has been followedin the past has been to design a system in which every component is aspecial-purpose device useful solely in cooperation with the otherspecial-purpose devices for computing bowling scores. This seeminglylogical approach has resulted in scoring systems which are unnecessarilycomplex and unnecessarily expensive to build and maintain.

SUMMARY OF THE INVENTION According to an example of the presentinvention, an improved electronic automatic scoring system for aplurality of bowling lanes is constructed using a general-purposemini-computer having an alterable readonly memory containing a computerprogram. The program consists of sequences of instructions written tocontrol the calculation and display of bowling scores. An electronicmodule is provided for each pair of bow]- ing lanes, each moduleincludes a lane pair memory,

and all lane pair memories are connected to operate as the main memoryof the mini-computer. Electronic modules, and player consoles, can beadded to the system without complication whenever it may be desired toexpand the system to handle additional pairs of bowling lanes.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a schematic diagram of anautomatic bowling score computing and display system constructedaccording to the teachings of the invention;

FIG. 2 is a more detailed block diagram of a portion of the system shownin FIG. 1;

FIG. 3 is a block diagram of a general-purpose minicomputer suitable foruse in the system of FIG. 1; and

FIG. 4 is a block diagram of a lane pair memory used as a memory by thecomputer of FIG. 3 in the system of FIG. 1.

DESCRIPTION OF A PREFERRED EMBODIMENT Referring in greater detail toFIG. 1 of the drawing, three pairs of bowling lanes are represented at1A, 1B; 2A, 2B; and 3A, 3B. A pinfall sensor PS is located at the remoteend of each bowling lane. Each pinfall sensor PS provides a clockedseries of binary units on its output conductor 11 which indicates thenumbers of the pins which have been knocked down after a ball has beenrolled down the bowling lane or alley. While any pinfall sensorequipment may be employed, a suitable equipment is described in detailin a US. patent application Ser. No. 318,550 filed by Hugo Logemann, Jr.and Harold F. Dion on Dec. 26, 1972 now US. Pat. No. 3,847,394, issuedon Nov. 12, 1974, entitled Bowling Pin Detector and assigned to theassignee of the present application. The outputs of all pinfall sensorsPS are cabled to a common pinfall sensor electronics unit PSE from whichthe signals are transmitted at suitable timed intervals to appropriateones of player consoles PC PC and PC;,.

Each player console PC is located at the player end of a pair of bowlinglanes and includes a cathode-raytube display device D, a keyboard KB anda logic unit L. The display device D is preferably a conventionaltelevision receiver which has been somewhat modified for use as adisplay device for alpha-numeric scoresheet information.

Each player console PC also includes a keyboard KB by means of which thefollowing transactions can be introduced into the system: (a) PlayerName Entry, (b) Handicap Entry, (c) Missing Player Entry, ((1) ScoreCorrection Entry, (e) Score Clear, (f) Lane Clear, and (g) PinfallEntry. The keyboard KB consists of a push button matrix providing anoutput that is applied to a coder 12 (FIG. 2) in a logic unit L. Thecoder 12 has a number of output lines 13, and the pushing of a buttonresults in a coded energization of appropriate ones of the output lines.The output lines are connected to the inputs of a corresponding numberof stages of a transmit shift register TSR. The transmit shift registeris constructed so that its contents can be shifted out in serial formthrough a switch 14 to a player console output line 15.

The logic unit L in player console PC also receives serially-presentedpinfall information signals on lead 16 from the pinsensor electronicsPSE. This serial signal is fed into the input of a pinfall buffer shiftregister PFB. Information stored in the buffer may be read out seriallythrough line 17 and switch 14 to player console output line 15.

The output lines 15 in FIG. 1 from player console PC, are connected to aplayer console interface PCI in respective electronics modules MOD. Theplayer console interface PCI in each electronics module is an interfacebetween a player console PC and a lane pair memory LPM in theelectronics module. Each lane pair memory LPM is a conventional knownsemiconductor random access memory consisting of 1024 words of eightbits each. The memory is made using eight semiconductor chips eachhaving storage locations for 1024 bits. Each semiconductor chip includesan address decoder responsive to 10 input address bit lines ADDR (FIG.2) and operative to select one of the 1024 bit storage locations on thechip. The same address is simultaneously applied to all eight chips toaccess 8 bit storage locations constituting one eight-bit memory wordstorage location. The eight data lines of the lane pair memory aredesignated DATA.

A player console interface PCI with the lane pair memory includes aserial-to-parallel converter SPC (FIG. 2) for the serial pinfall andother information received over line 15 from the player console. Theparallel output lines 19 from the SPC are connected to the respectivememory data lines DATA of the lane pair memory LPM. The player consoleinterface also includes a word framing logic WFL which senses the startbit of a word received on lines 15, and transmits a write enable signalover line 21 to the memory LPM when an 8-bit word is accumulated inconverter SPC. The information supplied from the serial-to-parallelconverter SPC is read into a storage location in memory LPMdetermined'by the address in a counter CF R in the timing unit T. Theaddress is passed through gate 22 when enabled by a memory cycle signalB.

The lane pair memories LPM in the electronic modules MOD in FIG. 1 areall connected by means of a multiconductor bus B and a memory interfaceMI with a general purpose mini-computer or processor PROC in a centralcontrol unit CC. As shown in FIG. 2, the memory interface Ml includes anaddress register AR, which is a serial-to-parallel converter, and towhich addresses are supplied in serial form over line 23 from theprocessor. Pin address bits are applied in parallel from register ARthrough gate 24 and over pin conductors 25 to the address input linesADDR of lane pair memory LPM. A lO-bit address from the processor PROCcan address any one of the 1024 word locations in the memory LPM. On theother hand, the remaining 6 bits in address register AR are applied to adecoder DEC, from which one output line 26 is applied through gate 28 tothe chip enable input of one respective lane pair memory LPM.

The memory interface Ml also includes an eightbit data register MDRconnected by eight parallel conductors 27 with the eight data lines DATAof the lane pair memory LPM. The data register MDR is aserial-toparallel converter and a parallel-to-serial converter. Eightdata bits applied from memory LPM over parallel lines 27 to dataregister DR are transferred serially over line 29 to the processor PROC.And, eight serial bits applied over line 31 to register MDR aretransmitted over parallel lines 27 to the data lines DATA of memory LPM.

Each electronics module MOD in FIG. 1 also includes a charactergenerator CG and a video mixer VM. Each character generator, as shown inFIG. 2, includes a character generator read-only memory CGM connected toreceive eight-bit data words from memory LPM over lines 33. Each suchdata Word is applied as an address to the read-only memory CGM. Thedigital information bits in the addressed location are applied inparallel over lines 35 to a video shift register, or parallel-to-serialconverter VSR. The contents of the converter VSR is shifted out onserial output lead 37 as a digitally-generated video signal. That is,the signal on lead 37 is a pattern of pulses and spaces existing in timesequence such that it can be used to control the intensity of theelectron beam in a cathode-ray tube and thus trace one line of ablack-and-white line image (no gray scale) on the face of the tube. Thesignal on lead 37 is thus a video signal for tracing a part of analphanumeric character corresponding to a conventional digitalrepresentation of the character supplied from the data output DATA oflane pair memory LPM to the address input of character generatorread-only memory CGM.

The digitallygenerated video signal on line 37 is applied to a videomixer VM, which also receives horizontal and vertical synchronizingsignals, and signals for creating a crossed line score sheet pattern onthe display, from the timing unit T over line 39. The video signal, thesynchronized pulses, and the crossed line signal are mixed to produce anoutput video signal on lead 41 which is a standard television videosignal suitable for application to the video circuit of a televisionreceiver. The signal is applied over lead 41 to a display device D inthe player console PC (FIG. 1 the display device D being a slightlymodified television receiver. The video signal on line 37 is alsoapplied over line 43 to a selector SEL in the central control unit CC.

Each one of the electronics modules MOD is needed for a correspondingbowling lane pair. The modules are constructed exactly alike, and anyreasonable number of modules can be connected into the system, that is,an electronics module (and player console) can be added to the systemfor every bowling lane pair that is added to the bowling establishment,without requiring any changes in, or substitution of, the centralcontrol unit CC.

The central control unit CC (FIG. 1) includes a proprietors controlconsole PCC by which the proprietor manages the operation of the bowlingestablishment through its automatic scoring system. The proprietorscontrol console includes a thumb wheel by which the proprietor controlsthe digital video selector SEL to select the video signal from theelectronics module corresponding to any desired bowling lane pair. Theselected video signal is combined with horizontal and verticalsynchronizing pulses in a video mixer VM and is then applied over line44 to a proprietors display device D, which is the same as the displaydevice D in the player consoles PC. The video signal from mixer VM isalso applied over line 45 to a printer PTR. The printer PTR includes acathode-ray-tube display on the face of which appears the same scoresheet information as appears on the display device D. The printer alsoincludes means to make a hard copy of the displayed score sheet on apiece of paper by any suitable method such as the xerographic method.

The proprietors control console PCC includes a control panel and logicby which commands are sent over lines 46 between the console FCC and thecomputer processor PROC. For example, the proprietor can des ignate eachbowling lane as having a status of of league, open, or practice". Theproprietors console has switches to accomplish score clear", lane clear,and print score functions. And players names for any desired lanes canbe entered. All of these controls and others are accomplished by signalsover lines 46 to the processor PROC.

A central timing unit T controls the timing of the entire system bysupplying various timing signals, designated t, to all units of thesystem.

The central control unit CC includes a general purpose mini-computerPROC and read-only memory ROM, as shown in more detail in FIG. 3. Theread-only memory ROM is a semiconductor memory containing computerinstruction words l6-bits long. Instructions are read out of the memoryunder control of addressing circuits including a program counter PCTR,an extended program counter PCB and a program counter control CC. Theinstructions are read out in sequence, except when a jump to anoutof-sequence instruction is effected by conventional logic in thecomputer processor. Instructions are read out to a 16-bit instructionregister IR. There are eight types of instructions: Unconditional jump,Jump and save, Logic function, Arithmetic function, Control and test,Load immediate, Add immediate, and And immediate.

Portions of an instruction in the instruction register IR are applied toan operation decoder OP, a destination decoder DD, and a source decoderSD, which provide output signals to control transfers from one place toanother in the systems. Another function portion of an instruction inregister IR is applied to an arithmetic unit AU together with theoperation code, to control all functions performed on data present onbusses A and B. The functions include: Add with carry, Subtract withcarry, Left shift with carry, Gray to Binary with carry, Add, Subtract,Left shift, and Gray to binary, Logical AND, Exclusive OR, Inclusive OR.Complement, Rotate right, Transfer and Compare. The result is suppliedto bus C. Eight-bit-word general registers GR-0 to GR-7 are connectedwith the busses and can be used by the computer programmerfor thetemporary storage of any type of information as needed in the executionof the computer program by which bowling scores are automaticallycomputed and displayed..Data words handled by the processor containeight bits and are transferred on busses A, B, C in bit serial form.Timing signals are provided by an-oscillator OSC and clock CLK whichprovide two-phase clock signals TBA and TBB used for the basic timing ofthe processor. A bit time generator BTG produces 12 timing pulses tocontrol status level functions during execution of each instruction. i

FIG. 4 shows one of the lane pair memories LPM included in the system ofFIG. 1, and thememory interface Ml included in the central control unitCC. The memory address register consists of an X address register XARand a Y address register YAR. Eight address bits from register XAR andtwo address bits from register YAR are applied through an address gatingunit G to a decoder in the memory LPM to select one eight-bit wordlocation from the 1024 word locations, in the memory LPM. Six bits fromregister YAR are applied to an address decoder AD to select one lanepair memory LPM from the plurality of up to 64 similar lane pairmemories in the system. Eight-bit memory words are read to and from thememory via a memory data register MDR. Data words are transferred in bitserial form between the memory register MDR and the data bussesconnected to the computer processor PROC.

The memory control unit MC in FIG. 4 controls the I cyclic operation ofthe lane pair memory LPM in synchronism with timing and control signalssupplied thereto over leads 47. There are two alternating memory accesscycles A and B during each bit time pulse from the bit timing generatorBTG in FIG. 3. Memory cycles A can be used by the processor PROC shownin FIGS. 1, 2 and 3. During memory cycles B a digital word is read outfrom the memory to the respective character generator CG, shown in FIGS.1 and 2, where it is converted into a video signal to refresh the scoresheet display on the'respective cathode fray tube display device D.During field retrace in the display device D, memory cycles B can beused to store information in the lane pair memory from the correspondingplayer console.

In the operation of the automatic scoring system, the proprietor actingthrough the proprietors control console PCC energizes a particular lanepair for bowlers in a league, open, or practice mode. The players namesare then entered, from the keyboard KB at the players console PC, to thelane pair memory LPM during memory cycles B of the memory. Each lanepair memory has storage space reserved for the names of players usingthe corresponding pair of lanes, and their scores for bowling frames 1through 10. Once the lane pair is put in operation, the display D in theplayer console PC is automatically and periodically refreshed with theinformation, such as players names, contained in the lane pair memoryduring the memory cycles B of the memory.

As' pinfall information is introduced,automatically by the pinfallsensors PS or-manually from the players console PC, this information fora given player is supplied to a nondisplayed storage location reservedfor.- information from a respective player console in the lane pairmemory during a memory cycle B of the memory. During memory cycles A,the processor continuously scans these non-displayed memory locations,

player, to compute the score that should be displayed" for that framefor the particular player. The score for the frame is then transferredto a prescribed location in' g the displayed portion of the lane pairmemory LPM. All these memory accesses by the processor are done duringmemory cycles A of the memory. During memory cycles B of the memory, theentire score sheet information stored in the displayed portion of thememory, including the score for the frame just computed, is read out ofthe memory to the character generator CG where the digital informationis translated to a video signal suitable for tracing the score sheetinformation on the face OfacathOde-ray-tube display D.

In this way, the scores of a player in each successive frame of a gameare computed and displayed. At the same time, the scores of all otherplayers on the two lanes are computed and displayed as the balls arerolled. And, at the same time, the scores of all the players on all theother lane pairs are computed and displayed at the respective playerconsoles. The single, general-purpose computer processor PROC handlesthe computations for the many players and many frames in a time divisionmultiplex fashion. The processor PROC accomplishes the computation ofeach frame score so rapidly that it has time to handle the scores for upto 12 bowlers bowling on each of up to 64 pairs of bowling lanes.

Provision is made for correcting an error in a players score. An errormay occur as the result of a human error when operating in thesemi-automatic mode, and as the result of unusual pin action whenoperating in the automatic mode. For example, a pin may be shiftedsideways by the ball to such an extent that it cannot be recognized as astanding pin by the pinfall sensor. An erroneous score in any frame iscorrected by transferring the correct score for the frame from theplayer console to the message receiving area in the lane pair memory.The processor recognizes the error correcting message, and requests ahard copy print of the existing score sheet information. While the printis being made, new pinfall information resulting from continued bowlingis accummulated in a queue in the lane pair memory. When the print isfinished, the processor recomputes the correct scores in the frame inwhich the correction was inserted, and preceeding frames if they areaffected, and in succeeding frames. The corrected scores are stored bythe processor in the appropriate displayed information storage region ofthe respective lane pair memory. Then the queued pinfall information isprocessed to compute scores for frames bowled after the error wascorrected. Then the score sheet information displayed contains thefully-corrected up-to-date scores, the correction having beenaccomplished without any delay to the bowlers.

Provision is made for a pacer player to even up the number of players ontwo competing teams. The pacers name is entered with a sign in front ofthe name. The pacers scores are displayed, but not included in the teamscore total. Provision is also made for a missing player. The playersaverage score is inserted in the tenth frame. These features of thesystem are accomplished by appropriate program routines stored in theread-only-memory ROM.

When a game on a lane pair is finished, a team captain pushes a scoreclear button on the player console. This causes the score clearinformation to be transferred from the player console to the lane pairmemory. The processor recognizes the order, and checks to make sure thegame is finished, and then causes a hard copy of the score sheetinformation to be made by the printer PTR. Then the scores for frames 1through 10 are erased from the lane pair memory, and consequently fromthe displayed score sheet information. The pressing of a lane clearbutton on the player console causes a clearing of the players names fromthe displayed score sheet.

When the players are relieved of the onerous scorekeeping task, thebowling games proceed much more rapidly, and the increased revenue forthe bowling establishment more than pays for the automatic scoringsystem.

What is claimed is:

l. A semiautomatic scoring system for a plurality of pairs of bowlinglanes comprising:

a player console for each pair of bowling lanes, including acathode-ray-tube display device, a keyboard and a logic unit,

an electronic module for each pair of bowling lanes,

including a lane-pair memory and a character generator, I

said keyboard in each player console being connected to supply playerand pinfall information in the form of digital signals through saidlogic unit in the player console to the lane-pair memory in therespective electronic module,

said character generator in each electronic module being constructedtotranslate digital information received from the corresponding lane-pairmemory into video signals and to supply the video signals to the displaydevice in the respective player console, and

a central control unit for all bowling lanes including a proprietorscontrol console, a proprietors cathode-ray-tube display device, adisplayedinformation printer unit, a lane-pair video signal selector toconnect the video signal from the character generator associated withany desired one of said bowling lane pairs to said proprietors displaydevice and said printer unit, a general purpose mini-computer processorconnected through a memory interface with all of said lane-pair memoriesso that they serve as the main memory for said processor, and aread-only memory containing a computer program for controlling theoperation of the processor in the computing and display of scores in allbowling lanes.

2. A fully automatic scoring system for a plurality of pairs of bowlinglanes, comprising:

a player console for each pair of bowling lanes, including acathode-ray-tube display device, a keyboard and a logic unit,

an electronic module for each pair of bowling lanes,

including a lane-pair memory and a character generator,

said keyboard in each player console being connected to supply playerand score correcting information in the form of digital signals throughsaid logic unit in the player console to the lane-pair memory in therespective electronic module,

a separate, automatic pinfall sensor for each of said bowling lanesconnected to supply pinfall information in electrical form through thelogic unit of the corresponding player console to the lane-pair memoryin the electronic module associated with that player console,

said character generator in each electronic module being constructed totranslate digital information received from the corresponding lane-pairmemory into video signals and to supply the video signals to the displaydevice in the respective player console, and

a central control unit for all bowling lanes including a proprietorscontrol console, a proprietors cathode-ray-tube display device, adisplayedinformation printer unit, a lane-pair video signal selector toconnect the video signal from the character generator associated withany desired one of said bowling lane pairs to said proprietors displaydevice and said printer unit, a general purpose mini-computer processorconnected through a memory interface with all of said lane-pair memoriesso that they serve as the main memory for said processor, and aread-only memory containing a computer program for controlling theoperation of said processor in the computing and display of scores inall bowling lanes.

1. A semiautomatic scoring system for a plurality of pairs of bowlinglanes comprising: a player console for each pair of bowling lanes,including a cathode-ray-tube display device, a keyboard and a logicunit, an electronic module for each pair of bowling lanes, including alane-pair memory and a chaRacter generator, said keyboard in each playerconsole being connected to supply player and pinfall information in theform of digital signals through said logic unit in the player console tothe lane-pair memory in the respective electronic module, said charactergenerator in each electronic module being constructed to translatedigital information received from the corresponding lane-pair memoryinto video signals and to supply the video signals to the display devicein the respective player console, and a central control unit for allbowling lanes including a proprietor''s control console, a proprietor''scathode-ray-tube display device, a displayed-information printer unit, alanepair video signal selector to connect the video signal from thecharacter generator associated with any desired one of said bowling lanepairs to said proprietor''s display device and said printer unit, ageneral purpose mini-computer processor connected through a memoryinterface with all of said lane-pair memories so that they serve as themain memory for said processor, and a read-only memory containing acomputer program for controlling the operation of the processor in thecomputing and display of scores in all bowling lanes.
 2. A fullyautomatic scoring system for a plurality of pairs of bowling lanes,comprising: a player console for each pair of bowling lanes, including acathode-ray-tube display device, a keyboard and a logic unit, anelectronic module for each pair of bowling lanes, including a lane-pairmemory and a character generator, said keyboard in each player consolebeing connected to supply player and score correcting information in theform of digital signals through said logic unit in the player console tothe lane-pair memory in the respective electronic module, a separate,automatic pinfall sensor for each of said bowling lanes connected tosupply pinfall information in electrical form through the logic unit ofthe corresponding player console to the lane-pair memory in theelectronic module associated with that player console, said charactergenerator in each electronic module being constructed to translatedigital information received from the corresponding lane-pair memoryinto video signals and to supply the video signals to the display devicein the respective player console, and a central control unit for allbowling lanes including a proprietor''s control console, a proprietor''scathode-ray-tube display device, a displayed-information printer unit, alane-pair video signal selector to connect the video signal from thecharacter generator associated with any desired one of said bowling lanepairs to said proprietor''s display device and said printer unit, ageneral purpose mini-computer processor connected through a memoryinterface with all of said lane-pair memories so that they serve as themain memory for said processor, and a read-only memory containing acomputer program for controlling the operation of said processor in thecomputing and display of scores in all bowling lanes.